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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5510 Rev. 2, 12/2008
MPC5510
MAPBGA-208 MAPBGA-225 17 mm x 17 mm 15 mm x 15 mm LQFP-144 QFN12 20 mm x 20 ##_mm_x_##mmmm LQFP-176 24 mm x 24 mm PKG-TBD ## mm x ## mm
MPC5510 Microcontroller Family Data Sheet
MPC5510 Family Features * Single issue, 32-bit CPU core complex (e200z1) - Compliant with the Power ArchitectureTM embedded category - Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. * Up to 1.5-Mbyte on-chip flash with flash control unit (FCU) * Up to 80 Kbytes on-chip SRAM * Memory protection unit (MPU) with up to sixteen region descriptors and 32-byte region granularity * Interrupt controller (INTC) capable of handling selectable-priority interrupt sources * Frequency modulated Phase-locked loop (FMPLL) * Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters * 16-channel enhanced direct memory access controller (eDMA) * Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI) * Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS200) * Up to 40-channel 12-bit analog-to-digital converter (ADC) * Up to four serial peripheral interface (DSPI) modules * Media Local Bus (MLB) emulation logic (works with two DSPIs, the e200z0, the eDMA, and system RAM to create a 3-pin or 5-pin 256Fs MLB protocol) * Up to eight serial communication interface (eSCI) modules * Up to six enhanced full CAN (FlexCAN) modules with configurable buffers * One inter IC communication interface (I2C) module
SOT-343R ##_mm_x_##mm
TBD
* Up to 144 configurable general purpose pins supporting input and output operations and 3.0V through 5.5V supply levels * Real-time counter (RTC_API) with clock source from external 32-kHz crystal oscillator, internal 32-kHz or 16-MHz oscillator and supporting wake-up with selectable 1-second resolution and > 1-hour timeout, or 1-millisecond resolution with maximum timeout of one second * Up to eight periodic interrupt timers (PIT) with 32-bit counter resolution * Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard * Device/board test support per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) * On-chip voltage regulator (VREG) for regulation of 5V input to 1.5V and 3.3V internal supply levels * Optional e200z0, second Power Architecture based I/O processor with VLE instruction set * Optional FlexRAY controller * Optional external bus interface (EBI) module
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2007, 2008. All rights reserved. Preliminary--Subject to Change Without Notice
Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4 1.1 Signal Properties and Multiplexing Summary . . . . . . . . .4 1.2 Power and Ground Supply Summary . . . . . . . . . . . . . .15 1.3 Pinout - 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.4 Pinout - 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 Pinout - 208 PBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 2.2.1 General Notes for Specifications at Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .21 2.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .25 2.5 Operating Current Specifications . . . . . . . . . . . . . .27 2.6 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .29 2.7 Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . . .30 2.8 Oscillators Electrical Characteristics. . . . . . . . . . . . . . .31 2.9 FMPLL Electrical Characteristics . . . . . . . . . . . . . . . . .33 2.10 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . .34 2.11 Flash Memory Electrical Characteristics. . . . . . . . . . . .35 2.12 Pad AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .36 2.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.13.1 Reset and Boot Configuration Pins . . . . . . . . . .37 2.13.2 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . .37 2.13.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . . .38 2.13.4 Nexus Debug Interface . . . . . . . . . . . . . . . . . . .41 2.13.5 External Bus Interface (EBI) . . . . . . . . . . . . . . .43 2.13.6 Enhanced Modular I/O Subsystem (eMIOS) . . .46 2.13.7 Deserial Serial Peripheral Interface (DSPI) . . . .47 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator . . . 32 Table 14. FMPLL Electrical Specifications . . . . . . . . . . . . . . . . . 33 Table 15. eQADC Conversion Specifications (Operating) . . . . . . 34 Table 16. Flash Program and Erase Specifications . . . . . . . . . . . 35 Table 17. Flash EEPROM Module Life (Full Temperature Range) 35 Table 18. Pad AC Specifications (VDDE = 3.0V - 5.5V) . . . . . . . 36 Table 19. Reset and Boot Configuration Timing . . . . . . . . . . . . . 37 Table 20. IRQ/NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 21. JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 22. Nexus Debug Port Timing . . . . . . . . . . . . . . . . . . . . . . 41 Table 23. External Bus Operation Timing . . . . . . . . . . . . . . . . . . 43 Table 24. eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 25. DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 26. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 27. Revision History of MPC5510 Data Sheet . . . . . . . . . . 53
2
List of Figures
F. . . . . . . . . . . . . . . . . Figure 1. MPC5510 Family Block Diagram 3 Figure 2. MPC5510 Pinout - 144 LQFP . . . . . . . . . . . . . . . . . . . 17 Figure 3. MPC5510 Pinout - 176 LQFP . . . . . . . . . . . . . . . . . . . 18 Figure 4. MPC5510 Pinout - 208 PBGA . . . . . . . . . . . . . . . . . . . 19 Figure 5. Pad Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6. Reset and Boot Configuration Timing. . . . . . . . . . . . . . 37 Figure 7. IRQ and NMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 8. JTAG Test Clock Input Timing. . . . . . . . . . . . . . . . . . . . 38 Figure 9. JTAG Test Access Port Timing . . . . . . . . . . . . . . . . . . . 39 Figure 10. JTAG JCOMP Timing . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . 40 Figure 12. Nexus Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 13. Nexus TDI, TMS, TDO Timing . . . . . . . . . . . . . . . . . . 42 Figure 14. CLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 15. Synchronous Output Timing . . . . . . . . . . . . . . . . . . . . 44 Figure 16. Synchronous Input Timing . . . . . . . . . . . . . . . . . . . . . 45 Figure 17. Address Latch Enable (ALE) Timing . . . . . . . . . . . . . 46 Figure 18. DSPI Classic SPI Timing -- Master, CPHA = 0 . . . . . 48 Figure 19. DSPI Classic SPI Timing -- Master, CPHA = 1 . . . . . 48 Figure 20. DSPI Classic SPI Timing -- Slave, CPHA = 0 . . . . . . 49 Figure 21. DSPI Classic SPI Timing -- Slave, CPHA = 1 . . . . . . 49 Figure 22. DSPI Modified Transfer Format Timing -- Master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 23. DSPI Modified Transfer Format Timing -- Master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 24. DSPI Modified Transfer Format Timing -- Slave, CPHA = 0 51 Figure 25. DSPI Modified Transfer Format Timing -- Slave, CPHA = 1 51 Figure 26. DSPI PCS Strobe (PCSS) Timing . . . . . . . . . . . . . . . 51
3 4
List of Tables
Table 1. MPC5510 Signal Properties . . . . . . . . . . . . . . . . . . . . . . .4 Table 2. MPC5510 Power/Ground . . . . . . . . . . . . . . . . . . . . . . . .15 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . .20 Table 4. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 5. ESD Ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 6. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . .25 Table 7. Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 8. I/O Pad Average DC Current . . . . . . . . . . . . . . . . . . . . . .29 Table 9. Low Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 10. 3.3V High Frequency External Oscillator. . . . . . . . . . . .31 Table 11. 5V Low Frequency (32 kHz) External Oscillator . . . . . .31 Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator . . .32
MPC5510 Microcontroller Family Data Sheet, Rev. 2 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Oscillators e200z1 Core Integer Execution Unit Multiply Unit Instruction Unit PPC & VLE General Purpose Registers (32 x 32-bit) Timers JTAG Branch Unit Load/Store Unit FlexRay Instruction Bus Data Bus eDMA Instruction Unit VLE NDI
FMPLL
VREG
MPC5510
INTC e200z0 Core Integer Execution Unit Multiply Unit General Purpose Registers (32 x 32-bit)
Branch Unit Load/Store Unit
Crossbar Switch (XBAR) Private Instruction Bus Memory Protection Unit (MPU)
FCU Flash (ECC) eSCI
Peripheral Bridge EBI DSPI I2C FlexCAN
RAM Controller SRAM (ECC)
ADC
BAM
eMIOS200
SIU
PIT
MLB
LEGEND
ADC BAM EBI ECC DSPI eDMA eMIOS200 eSCI FCU FlexCAN - Analog to Digital Converter modules - Boot Assist Module - External Bus Interface module - Error Correction Code - Serial Peripherals Interface controller module - enhanced Direct Memory Controller module - Timed Input Output module - Serial Communications Interface modules - Flash Controller Unit - Controller Area Network controller modules FlexRay - Dual Channel FlexRay controller FMPLL - Frequency Modulated Phase Locked Loop module I 2C - Inter IC Controller modules INTC - Interrupt Controller module JTAG - Joint Test Action Group interface MLB - Media Local Bus emulation logic NDI - Nexus Debug Interface module PIT - Periodic Interrupt Timer module SIU - System Integration module VREG - Voltage Regulator
Figure 1. MPC5510 Family Block Diagram
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
Pin Assignments and Reset States
1
1.1
Pin Assignments and Reset States
Signal Properties and Multiplexing Summary
Table 1 shows the signal properties for each pin on the MPC5510. For all port pins, which have an associated pad configuration register (SIU_PCRn register) to control its pin properties, the "Supported Pin Functions" column lists the functions associated with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, Function1, Function2 and Function3. If fewer than three functions plus GPIO are supported by a given pin, then the unused functions begin with Function3, then Function2, then Function1. Note that the GPIO number is the same number as the corresponding pad configuration register (SIU_PCRn) number. Table 1. MPC5510 Signal Properties
GPIO Pin (PCR) Name Num1 Supported Functions2 Pad4 I/O Voltage3 Type Type Status During Reset5 Status After Reset5 Package Pin Locations 144 176 208
Description
Port A (16) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 PA0 AN0 PA1 AN1 PA2 AN2 PA3 AN3 PA4 AN4 PA5 AN5 PA6 AN6 PA7 AN7 PA8 AN8/ANW PA9 AN9/ANX PA10 AN10/ANY PA11 AN11/ANZ PA12 AN12 PA13 AN13 PA14 AN14 EXTAL326 GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input GPI eQADC Analog Input 32 kHz Crystal Oscillator Input I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH AE + IH -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 8 7 6 5 4 3 2 143 142 140 139 138 137 9 8 7 6 5 4 3 2 175 174 172 171 170 169 E3 E2 E1 D3 D2 D1 C2 C1 A3 C4 D5 C5 B5 A5
PA14
14
VDDA
AE + IH
--
--
136
167
D6
MPC5510 Microcontroller Family Data Sheet, Rev. 2 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PA15 AN15 XTAL326
Description
Pad4 I/O Voltage3 Type Type
I I O
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
135 165 C6
PA15
15
GPI eQADC Analog Input 32 kHz Crystal Oscillator Output
VDDA
AE + IH
--
--
Port B (16) PB0 AN28 eMIOS16 PCS_C5 PB1 AN29 eMIOS17 PCS_C4 PB2 AN30 eMIOS18 PCS_C3 PB3 AN31 PCS_C2 PB4 AN32 PCS_C1 PB5 AN33 PCS_C0 PB6 AN34 SCK_C PB7 AN35 SOUT_C PB8 AN36 SIN_C PB9 AN37 CNTX_D PCS_B4 PB10 AN38 CNRX_D PCS_B3 PB11 AN39 eMIOS19 PCS_B5 GPIO eQADC Analog Input7 eMIOS Channel DSPI_C Peripheral Chip Select GPIO eQADC Analog Input7 eMIOS Channel DSPI_C Peripheral Chip Select GPIO eQADC Analog Input7 eMIOS Channel DSPI_C Peripheral Chip Select GPIO eQADC Analog Input7 DSPI_C Peripheral Chip Select GPIO eQADC Analog Input7 DSPI_C Peripheral Chip Select GPIO eQADC Analog Input7 DSPI_C Peripheral Chip Select GPIO eQADC Analog Input7 DSPI_C Clock GPIO eQADC Analog Input7 DSPI_C Data Output GPIO eQADC Analog Input7 DSPI_C Data Input GPIO eQADC Analog Input7 CAN_D Transmit DSPI_B Peripheral Chip Select GPIO eQADC Analog Input7 CAN_D Receive DSPI_B Peripheral Chip Select GPIO eQADC Analog Input7 eMIOS Channel DSPI_B Peripheral Chip Select I/O I O O I/O I O O I/O I O O I/O I O I/O I O I/O I I/O I/O I I/O I/O I O I/O I I I/O I O O I/O I I O I/O I O O
PB0
16
VDDE1
A + SH
--
--
134
162
C7
PB1
17
VDDE1
A + SH
--
--
133
161
D7
PB2
18
VDDE1
A + SH
--
--
132
160
A8
PB3
19
VDDE1
A + SH
--
--
131
159
B8
PB4
20
VDDE1
A + SH
--
--
130
158
C8
PB5
21
VDDE1
A + SH
--
--
129
157
D8
PB6
22
VDDE1
A + SH
--
--
128
156
A9
PB7
23
VDDE1
A + SH
--
--
127
153
B9
PB8
24
VDDE1
A + SH
--
--
126
152
C9
PB9
25
VDDE1
A + SH
--
--
125
151
D9
PB10
26
VDDE1
A + SH
--
--
124
150
A10
PB11
27
VDDE1
A + SH
--
--
123
149
B10
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PB12 TXD_G PCS_B4 PB13 RXD_G PCS_B3 PB14 TXD_H PB15 RXD_H
Description
Pad4 I/O Voltage3 Type Type
I/O O O I/O I O I/O O I/O I Port C (16)
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
-- 164 A7
PB12
28
GPIO SCI_G Transmit DSPI_B Peripheral Chip Select GPIO SCI_G Receive DSPI_B Peripheral Chip Select GPIO SCI_H Transmit GPIO SCI_H Receive
VDDE1
SH
--
--
PB13
29
VDDE1
SH
--
--
--
163
B7
PB14 PB15
30 31
VDDE1 VDDE1
SH SH
-- --
-- --
-- --
148 147
C10 A11
PC0
32
PC0 eMIOS0 FR_A_TX_EN AD24 PC1 eMIOS1 FR_A_TX AD16 PC2 eMIOS2 FR_A_RX TS PC3 eMIOS3 FR_DBG0 PC4 eMIOS4 FR_DBG1 PC5 eMIOS5 FR_DBG2 PC6 eMIOS6 FR_DBG3 PC7 eMIOS7 FR_B_RX PC8 eMIOS8 FR_B_TX AD15 PC9 eMIOS9 FR_B_TX_EN AD14
GPIO eMIOS Channel FlexRay Channel A Transmit Enable EBI Muxed Address/Data GPIO eMIOS Channel FlexRay Channel A Transmit EBI Muxed Address/Data GPIO eMIOS Channel FlexRay Channel A Receive EBI Transfer Start GPIO eMIOS Channel FlexRay Debug GPIO eMIOS Channel FlexRay Debug GPIO eMIOS Channel FlexRay Debug GPIO eMIOS Channel FlexRay Debug GPIO eMIOS Channel FlexRay Channel B Receive GPIO eMIOS Channel FlexRay Channel B Transmit EBI Muxed Address/Data GPIO eMIOS Channel FlexRay Channel B Transmit Enable EBI Muxed Address/Data
I/O I/O O I/O I/O I/O O I/O I/O I/O I I/O I/O I/O O I/O I/O O I/O I/O O I/O I/O O I/O I/O I I/O I/O O I/O I/O I/O O I/O
VDDE1
MH
--
--
122
146
B11
PC1
33
VDDE1
MH
--
--
121
145
C11
PC2
34
VDDE1
MH
--
--
120
144
D11
PC3
35
VDDE1
MH
--
--
117
141
A12
PC4
36
VDDE1
SH
--
--
116
140
B12
PC5
37
VDDE1
SH
--
--
115
139
C12
PC6
38
VDDE1
SH
--
--
114
138
D12
PC7
39
VDDE1
SH
--
--
113
137
A13
PC8
40
VDDE1
MH
--
--
112
136
B13
PC9
41
VDDE1
MH
--
--
111
135
C13
MPC5510 Microcontroller Family Data Sheet, Rev. 2 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PC10 eMIOS10 PCS_C5 SCK_D PC11 eMIOS11 PCS_C4 SOUT_D PC12 eMIOS12 PSC_C3 SIN_D PC13 eMIOS13 PCS_A5 PCS_D0 PC14 eMIOS14 PCS_A4 PCS_D1 PC15 eMIOS15 PCS_A3 PCS_D2
Description
Pad4 I/O Voltage3 Type Type
I/O I/O O I/O I/O I/O O O I/O I/O O I I/O I/O O O I/O I/O O O I/O I/O O O
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
PC10
42
GPIO eMIOS Channel DSPI_C Peripheral Chip Select DSPI_D Clock GPIO eMIOS Channel DSPI_C Peripheral Chip Select DSPI_D Serial Out GPIO eMIOS Channel DSPI_C Peripheral Chip Select DSPI_D Serial In GPIO eMIOS Channel DSPI_A Peripheral Chip Select DSPI_D Peripheral Chip Select GPIO eMIOS Channel DSPI_A Peripheral Chip Select DSPI_D Peripheral Chip Select GPIO eMIOS Channel DSPI_A Peripheral Chip Select DSPI_D Peripheral Chip Select
VDDE1
SH
--
--
110
134
A14
PC11
43
VDDE1
SH
--
--
109
133
B14
PC12
44
VDDE1
SH
--
--
108
132
B16
PC13
45
VDDE1
SH
--
--
107
131
C15
PC14
46
VDDE1
SH
--
--
106
130
C16
PC15
47
VDDE1
SH
--
--
105
129
D14
Port D (16) PD0 CNTX_A PCS_D3 PD1 CNRX_A PCS_D4 PD2 CNRX_B eMIOS10 BOOTCFG PCS_D5 PD3 CNTX_B eMIOS11 PD4 CNTX_C eMIOS12 PD5 CNRX_C eMIOS13 GPIO CAN_A Transmit DSPI_D Peripheral Chip Select GPIO CAN_A Receive DSPI_D Peripheral Chip Select GPIO CAN_B Receive eMIOS Channel Boot Configuration DSPI_D Peripheral Chip Select GPIO CAN_B Transmit eMIOS Channel GPIO CAN_C Transmit eMIOS Channel GPIO CAN_C Receive eMIOS Channel I/O O O I/O I O I/O I O I O I/O O O I/O O O I/O I O
PD0
48
VDDE1
SH
--
--
104
128
D15
PD1
49
VDDE1
SH
--
--
103
127
D16
PD2
50
VDDE1
SH
BOOTCFG (Pulldown)
GPI (Pulldown)
102
126
E14
PD3
51
VDDE1
SH
--
--
101
125
E15
PD4
52
VDDE1
SH
--
--
100
124
E16
PD5
53
VDDE1
SH
--
--
99
123
F13
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PD6 TXD_A eMIOS14 PD7 RXD_A eMIOS15 PD8 TXD_B SCL_A PD9 RXD_B SDA_A PD10 PCS_B2 CNTX_F NMI0 PD11 PCS_B1 CNRX_F NMI1 PD12 PCS_B0 eMIOS9 PD13 SCK_B eMIOS8 PD14 SOUT_B eMIOS7 PD15 SIN_B eMIOS6
Description
Pad4 I/O Voltage3 Type Type
I/O O O I/O I O I/O O I/O I/O I I/O I/O O O I I/O O I I I/O I/O O I/O I/O O I/O O O I/O I O Port E (16)
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
98 122 F14
PD6
54
GPIO SCI_A Transmit eMIOS Channel GPIO SCI_A Receive eMIOS Channel GPIO SCI_B Transmit I2C Serial Clock Line GPIO SCI_B Receive I2C Serial Data Line GPIO DSPI_B Peripheral Chip Select CAN_F Transmit NMI Input for Z1 Core GPIO DSPI_B Peripheral Chip Select CAN_F Receive NMI Input for Z0 Core GPIO DSPI_B Peripheral Chip Select eMIOS Channel GPIO DSPI_B Clock eMIOS Channel GPIO DSPI_B Data Output eMIOS Channel GPIO DSPI_B Data Input eMIOS Channel
VDDE1
SH
--
--
PD7
55
VDDE1
SH
--
--
97
121
F15
PD8
56
VDDE1
SH
--
--
94
118
G13
PD9
57
VDDE1
SH
--
--
93
117
F16
PD10
58
VDDE1
SH
--
--
92
116
G14
PD11
59
VDDE1
SH
--
--
91
115
G15
PD12
60
VDDE1
SH
--
--
90
114
H14
PD13
61
VDDE1
SH
--
--
89
113
H15
PD14
62
VDDE1
SH
--
--
88
110
J14
PD15
63
VDDE1
SH
--
--
87
107
K14
PE0
64
PE0 PCS_A2 eMIOS5 MLBCLK PE1 PCS_A1 eMIOS4 MLBSI / MLBSIG PE2 PCS_A0 eMIOS3 MLBDI / MLBDAT
GPIO DSPI_A Peripheral Chip Select eMIOS Channel MLB Clock GPIO DSPI_A Peripheral Chip Select eMIOS Channel MLB Signal In (5-pin) / MLB Bi-directional Signal (3-pin) GPIO DSPI_A Peripheral Chip Select eMIOS Channel MLB Data In (5-pin) / MLB Bi-directional Data (3-pin)
I/O O O I I/O O O I I/O I/O I/O O I I/O
VDDE1
SH
--
--
86
106
K16
PE1
65
VDDE1
MH
--
--
85
103
L14
PE2
66
VDDE1
MH
--
--
84
101
L15
MPC5510 Microcontroller Family Data Sheet, Rev. 2 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PE3 SCK_A eMIOS2 MLBSO /
Description
Pad4 I/O Voltage3 Type Type
I/O I/O O O O I/O O O O O I/O I O O O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port F (16)
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
PE3
67
GPIO DSPI_A Clock eMIOS Channel MLB Signal Out (5-pin) / MLBSIG_BUFEN MLB Signal Level Shifter Enable (3-pin) GPIO DSPI_A Data Out eMIOS Channel MLB Data Out (5-pin) / MLBDAT_BUFEN MLB Data Level Shifter Enable (3-pin) PE4 SOUT_A eMIOS1 MLBDO / PE5 SIN_A eMIOS0
MLB_SLOT / MLB_SIGOBS / MLB_DATOBS
VDDE1
MH
--
--
83
100
M13
PE4
68
VDDE1
MH
--
--
82
98
N14
PE5
69
GPIO DSPI_A Data In eMIOS Channel MLB Slot Debug / MLB Clock Adjust Observe Signal / MLB Clock Adjust Observe Data GPIO System Clock Output GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
VDDE1
MH
--
--
81
97
M15
PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15
70 71 72 72 74 75 76 77 78 79
PE6 CLKOUT PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15
VDDE3 VDDE1 VDDE1 VDDE1 VDDE1 VDDE1 VDDE1 VDDE1 VDDE1 VDDE1
MH SH SH SH SH SH SH SH SH SH
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
67 -- -- -- -- -- -- -- -- --
83 -- -- -- 112 111 109 108 102 99
P13 H13 H16 J13 J16 J15 K13 L13 L16 M14
PF0
80
PF0 RD_WR EVTI8 PF1 TA MLBCLK EVTO8 PF2 AD8 ADDR8 MLBSI / MLBSIG MSEO8
GPIO EBI Read/Write Nexus Event In GPIO EBI Transfer Acknowledge MLB Clock Nexus Event Out GPIO EBI Muxed Address/Data EBI Non Muxed Address MLB Signal In (5-pin) / MLB Bi-Directional Signal (3-pin) Nexus Message Start/End Out
I/O I/O I I/O I/O I O I/O I/O O I I/O O
VDDE3
MH
--
--
66
82
N12
PF1
81
VDDE3
MH
--
--
65
81
P12
PF2
82
VDDE3
MH
--
--
64
80
R12
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PF3 AD9 ADDR9 MLBDI / MLBDAT MCKO8
Description
Pad4 I/O Voltage3 Type Type
I/O I/O O I I/O O I/O I/O O O O O I/O I/O O O O O I/O I/O O O O O O I/O I/O O O I/O I/O O O I/O I/O O O I/O O O O I/O O I O I/O I/O O O
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
PF3
83
GPIO EBI Muxed Address/Data EBI Non Muxed Address MLB Data In (5-pin) / MLB Bi-directional Data (3-pin) Nexus Message Clock Out
VDDE3
MH
--
--
63
79
T12
PF4
84
GPIO PF4 EBI Muxed Address/Data AD10 EBI Non Muxed Address ADDR10 MLB Signal Out (5-pin) / MLBSO / MLBSIG_BUFEN MLB Signal Level Shifter Enable (3-pin) MDO08 Nexus Message Data Out PF5 AD11 ADDR11 MLBDO / MLBDAT_BUFEN MDO18 PF6 AD12 ADDR12 MLB_SLOT / MLB_SIGOBS / MLB_DATOBS MDO28 PF7 AD13 ADDR13 MDO38 PF8 AD14 ADDR14 MDO48 PF9 AD15 ADDR15 MDO58 PF10 CS1 TXD_C MDO68 PF11 CS0 RXD_C MDO78 PF12 TS TXD_D ALE GPIO EBI Muxed Address/Data EBI Non Muxed Address MLB Data Out (5-pin) / MLB Data Level Shifter Enable (3-pin) Nexus Message Data Out GPIO EBI Muxed Address/Data EBI Non Muxed Address MLB Slot Debug / MLB Clock Adjust Observe Signal / MLB Clock Adjust Observe Data Nexus Message Data Out GPIO EBI Muxed Address/Data EBI Non Muxed Address Nexus Message Data Out GPIO EBI Muxed Address/Data EBI Non Muxed Address Nexus Message Data Out GPIO EBI Muxed Address/Data EBI Non Muxed Address Nexus Message Data Out GPIO EBI Chip Select SCI_C Transmit Nexus Message Data Out GPIO EBI Chip Select SCI_C Receive Nexus Message Data Out GPIO EBI Transfer Start SCI_D Transmit EBI Address Latch Enable
VDDE3
MH
--
--
59
74
T10
PF5
85
VDDE3
MH
--
--
58
72
R9
PF6
86
VDDE3
MH
--
--
57
68
T8
PF7
87
VDDE3
MH
--
--
56
66
P8
PF8
88
VDDE2
MH
--
--
55
65
N8
PF9
89
VDDE2
MH
--
--
54
64
T7
PF10
90
VDDE2
MH
--
--
52
62
R7
PF11
91
VDDE2
MH
--
--
51
61
P7
PF12
92
VDDE2
MH
--
--
50
60
N7
MPC5510 Microcontroller Family Data Sheet, Rev. 2 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PF13 OE RXD_D PF14 WE0 BDIP CNTX_D PF15 WE1 TEA CNRX_D
Description
Pad4 I/O Voltage3 Type Type
I/O O I I/O O O O I/O O I/O I
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
49 59 R6
PF13
93
GPIO EBI Output Enable SCI_D Receive GPIO EBI Write Enable EBI Burst Data In Progress CAN_D Transmit GPIO EBI Write Enable EBI Transfer Error Acknowledge CAN_D Receive
VDDE2
MH
--
--
PF14
94
VDDE2
MH
--
--
45
55
P6
PF15
95
VDDE2
MH
--
--
44
54
N6
Port G (16) PG0 AD16 eMIOS16 PG1 AD17 eMIOS17 SIN_C PG2 AD18 eMIOS18 SOUT_C PG3 AD19 eMIOS19 SCK_C PG4 AD20 eMIOS20 PCS_C0 PG5 AD21 eMIOS21 PG6 AD22 eMIOS22 PG7 AD23 eMIOS23 RXD_C PG8 AD24 PCS_A4 GPIO EBI Muxed Address/Data eMIOS Channel GPIO EBI Muxed Address/Data eMIOS Channel DSPI_C Serial In GPIO EBI Muxed Address/Data eMIOS Channel DSPI_C Serial Out GPIO EBI Muxed Address/Data eMIOS Channel DSPI_C Serial Clock GPIO EBI Muxed Address/Data eMIOS Channel DSPI_C Peripheral Chip Select GPIO EBI Muxed Address/Data eMIOS Channel GPIO EBI Muxed Address/Data eMIOS Channel GPIO EBI Muxed Address/Data eMIOS Channel SCI_C Receive GPIO EBI Muxed Address/Data DSPI_A Peripheral Chip Select I/O I/O I/O I/O I/O I/O I I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O O
PG0
96
VDDE2
MH
--
--
43
51
P5
PG1
97
VDDE2
MH
--
--
42
50
T4
PG2
98
VDDE2
MH
--
--
41
49
R4
PG3
99
VDDE2
MH
--
--
40
48
P4
PG4
100
VDDE2
MH
--
--
39
47
T3
PG5
101
VDDE2
MH
--
--
38
46
R3
PG6
102
VDDE2
MH
--
--
37
45
T2
PG7
103
VDDE2
MH
--
--
36
44
R1
PG8
104
VDDE2
MH
--
--
35
43
P2
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PG9 AD25 PCS_A3 TXD_C PG10 AD26 PCS_A2 PG11 AD27 PCS_A1 PG12 AD28 PCS_A0 PG13 AD29 SCK_A PG14 AD30 SOUT_A PG15 AD31 SIN_A
Description
Pad4 I/O Voltage3 Type Type
I/O I/O O O I/O I/O O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I Port H (16)
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
PG9
105
GPIO EBI Muxed Address/Data DSPI_A Peripheral Chip Select SCI_C Transmit GPIO EBI Muxed Address/Data DSPI_A Peripheral Chip Select GPIO EBI Muxed Address/Data DSPI_A Peripheral Chip Select GPIO EBI Muxed Address/Data DSPI_A Peripheral Chip Select GPIO EBI Muxed Address/Data DSPI_A Clock GPIO EBI Muxed Address/Data DSPI_A Data Out GPIO EBI Muxed Address/Data DSPI_A Data In
VDDE2
MH
--
--
34
42
N3
PG10
106
VDDE2
MH
--
--
30
38
N2
PG11
107
VDDE2
MH
--
--
29
37
N1
PG12
108
VDDE2
MH
--
--
28
36
M4
PG13
109
VDDE2
MH
--
--
27
35
M3
PG14
110
VDDE2
MH
--
--
26
34
M2
PG15
111
VDDE2
MH
--
--
25
33
M1
PH0
112
PH0 AN27 eMIOS20 SCL_A PH1 AN26 eMIOS21 SDA_A PH2 AN25 eMIOS22 CS3 PH3 AN24 eMIOS23 CS2 PH4 AN23 TXD_E MA2 PH5 AN22 RXD_E MA1
GPIO eQADC Analog Input7 eMIOS Channel I2C_A Serial Clock GPIO eQADC Analog Input7 eMIOS Channel I2C_A Serial Data GPIO eQADC Analog Input7 eMIOS Channel EBI Chip Select GPIO eQADC Analog Input7 eMIOS Channel EBI Chip Select GPIO eQADC Analog Input7 SCI_E Transmit eQADC External Mux Address GPIO eQADC Analog Input7 SCI_E Receive eQADC External Mux Address
I/O I O I/O I/O I O I/O I/O I O O I/O I O O I/O I O O I/O I I O
VDDE2
A + SH
--
--
24
32
L3
PH1
113
VDDE2
A + SH
--
--
23
31
L2
PH2
114
VDDE2
A + MH
--
--
22
30
L1
PH3
115
VDDE2
A + MH
--
--
21
29
K4
PH4
116
VDDE2
A + SH
--
--
20
28
K3
PH5
117
VDDE2
A + SH
--
--
19
24
J3
MPC5510 Microcontroller Family Data Sheet, Rev. 2 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1 Supported Functions2
PH6 AN21 TXD_F PH7 AN20 RXD_F PH8 AN19 CNTX_E MA0 PH9 AN18/ANT CNRX_E PH10 AN17/ANS CNRX_F PH11 AN16/ANR CNTX_F PH12 PCS_D5 PH13 PH14 WE2 PH15 WE3
Description
Pad4 I/O Voltage3 Type Type
I/O I O I/O I I I/O I O O I/O I I I/O I I I/O I O I/O O I/O I/O O I/O O Port J (16)
Status During Reset5
Status After Reset5
Package Pin Locations 144 176 208
18 23 J2
PH6
118
GPIO eQADC Analog Input7 SCI_F Transmit GPIO eQADC Analog Input7 SCI_F Receive GPIO eQADC Analog Input7 CAN_E Transmit eQADC External Mux Address GPIO eQADC Analog Input7 CAN_E Receive GPIO eQADC Analog Input7 CAN_F Receive GPIO eQADC Analog Input7 CAN_F Transmit GPIO DSPI_D Peripheral Chip Select GPIO GPIO EBI Write Enable GPIO EBI Write Enable
VDDE2
A + SH
--
--
PH7
119
VDDE2
A + SH
--
--
17
22
J1
PH8
120
VDDE2
A + SH
--
--
14
17
H1
PH9
121
VDDE2
A + SH
--
--
13
14
G2
PH10
122
VDDE2
A + SH
--
--
12
12
F4
PH11
123
VDDE2
A + SH
--
--
11
11
F3
PH12 PH13 PH14 PH15
124 125 126 127
VDDE2 VDDE2 VDDE2 VDDE2
SH SH MH MH
-- -- -- --
-- -- -- --
-- -- -- --
-- -- 53 52
F2 F1 T5 R5
PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7
128 129 130 131 132 133 134 135
PJ0 AD0 PJ1 AD1 PJ2 AD2 PJ3 AD3 PJ4 AD4 PJ5 AD5 PJ6 AD6 PJ7 AD7
GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data GPIO EBI Muxed Address/Data
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
VDDE3 VDDE3 VDDE3 VDDE3 VDDE3 VDDE3 VDDE3 VDDE3
MH MH MH MH MH MH MH MH
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- 75 73 69 67
N11 P11 N10 R10 P10 T9 P9 R8
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO Pin (PCR) Name Num1
PJ8 PJ9 PJ10 PJ11 PJ12 PJ13 PJ14 PJ15 136 137 138 139 140 141 142 143
Supported Functions2
PJ8 PCS_D4 PJ9 PCS_D3 PJ10 PCS_D2 PJ11 PCS_D1 PJ12 PCS_D0 PJ13 SCK_D PJ14 SOUT_D PJ15 SIN_D
Description
Pad4 I/O Voltage3 Type Type
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I Port K (2)
Status During Reset5
-- -- -- -- -- -- -- --
Status After Reset5
-- -- -- -- -- -- -- --
Package Pin Locations 144 176 208
-- -- -- -- -- -- -- -- 27 26 25 19 18 16 15 13 K2 K1 J4 H3 H2 G4 G3 G1
GPIO DSPI_D Peripheral Chip Select GPIO DSPI_D Peripheral Chip Select GPIO DSPI_D Peripheral Chip Select GPIO DSPI_D Peripheral Chip Select GPIO DSPI_D Peripheral Chip Select GPIO DSPI_D Clock GPIO DSPI_D Serial Out GPIO DSPI_D Serial In
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2
SH SH SH SH SH SH SH SH
PK0 PK1
144 145
PK0 EXTAL32 PK1 XTAL32
GPIO 32 kHz Crystal Oscillator Input GPIO 32 kHz Crystal Oscillator Output
I I I O
VDDA VDDA
AE + IH AE + IH
-- --
-- --
-- --
168 166
B6 A6
Miscellaneous Pins (9) EXTAL XTAL TMS TCK TDO TDI JCOMP TEST10 RESET
1 2
-- -- -- -- -- -- -- -- --
EXTAL EXTCLK XTAL TMS TCK TDO TDI JCOMP TEST RESET
Main Crystal Oscillator Input External Clock Input Main Crystal Oscillator Output JTAG Test Mode Select Input JTAG Test Clock Input JTAG Test Data Output JTAG Test Data Input JTAG Compliancy Test Mode Select External Reset
I I O I I O I I I I/O
VDDSYN VDDSYN VDDE3 VDDE3 VDDE3 VDDE3 VDDE3 VDDE3 VDDE2
AE AE SH IH MH IH IH IH SH
EXTAL XTAL TMS (Pull Up) TCK (Pull Down) TDO (Pull Up ) TDI (Pull Up) JCOMP (Pull Down) TEST RESET (Pull Up)
9
75 74 72 71 70 69 68 62 10
91 90 88 87 86 85 84 78 10
N16 P16 T15 R14 T14 R13 T13 R11 E4
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number. This column lists the functions associated with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, function 1, function 2, and function 3. The unused functions by a given pin begin with function 3, then function 2, then function 1. 3 These are nominal voltages. Each segment provides the power and ground for the given set of I/O pins. 4 Pad types: SH - Bi-directional slow speed pad with input hysteresis; MH - Bi-directional medium speed pad with input hysteresis; IH - Input only pad with input hysteresis; AE/A - Analog pad. 5 A dash for the function in this column denotes the input and output buffer are turned off.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
6
Port A[14:15]--EXTAL32 and XTAL32 functions only apply on the 144LQFP. These functions are on PortK[0:1] for the 176LQFP and 208BGA. In the 176 LQFP and 208 BGA packages, activity on PA14 should be minimized if the 32kHz XTAL is enabled. 7 This analog input pin has reduced analog-to-digital conversion accuracy compared to PA0-PA15. See the MPC5510 Microcontroller Family Data Sheet for values. 8 The NEXUS function is selected when the JTAG TAP controller is enabled via the JCOMP pin and the appropriate bits in the NP PCR register. The value of the PA field in the associated PCR register has no effect on the pin function when the NEXUS function is selected. 9 Pullup is enabled only when JCOMP is negated. 10 Always connect the TEST pin to Ground (Vss).
1.2
Power and Ground Supply Summary
Table 2. MPC5510 Power/Ground
Pin Name
VDDR VDDA VRH2 VSSA VRL
3
Function Description
Voltage Regulator Supply Analog Power eQADC Voltage Reference High Analog Ground eQADC Voltage Reference Low eQADC Reference Bypass Capacitor Flash Program/Erase Power
Voltage1
5.0 V 5.0 V 46
Package Pin Locations 144 176 56 176 173 1 94 89 92
105,120, 143,155 21,41,58 71,77
208
T6 A2 B3 A4 B4 B1 P15 R16 M16 A15,D10,E13, G16,K15 H4,L4,N5,P1 N9,T11
144 5.0 V - 141 - VSSA 5.0 V 3.3 V - 1 78 73 76 96,119
REFBYPC VPP4 VDDSYN
5
Clock Synthesizer Power Clock Synthesizer Ground
VSSSYN VDDE1 VDDE2 VDDE3 VSSE1 VSSE2 VSSE3 VDD335 VFLASH
5, 6
External I/O Power
3.3 V - 5.0 V
16,33,48 61 95,118
104,119, Shorted to VSS in 142,154 the package 20,40,57 70,76 93 39,63,95 Shorted to VSS in the package Shorted to VSS in the package N15 A1,A16,B2,B15, R2,R15,T1,T16 Shorted to VDD in the package C3,C14,D4,D13, G7-G10,H7-H10, J7-J10,K7-K10, N4,N13,P3,P14 Shorted to VSS in the package
External I/O Ground
-
15,32,47 60
3.3 V I/O Power Flash Read Power Internal Logic Power
3.3 V
77 31,53,79
VDD5 VDDF5
1.5 V Flash Internal Logic Power 79
95
VSS
Ground - 80 96
VSSF
1 2
Flash Internal Logic Ground
These are nominal voltages. VRH is shorted to VDDA in the 144LQFP and 176 LQFP packages. MPC5510 Microcontroller Family Data Sheet, Rev. 2
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
15
Pin Assignments and Reset States
3 4
VRL is shorted to VSSA in the 144LQFP and 176 LQFP packages. VPP requires 5V for program/erase operations, but may be 0-5V otherwise. VPP should not go high or low when the device is in Sleep mode. 5 Voltage generated from internal voltage regulator and no external connection or load allowed except the required bypass capacitors. 6V FLASH is shorted to VDD33 in the package.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
1.3
Pinout - 144 LQFP
VDDA/VRH PA8/AN8/ANW PA9/AN9/ANX VSSA/VRL PA10/AN10/ANY PA11/AN11/ANZ PA12/AN12 PA13/AN13 PA14/AN14/EXTAL32 PA15/AN15/XTAL32 PB0/AN28/eMIOS16/PCS_C5 PB1/AN29/eMIOS17/PCS_C4 PB2/AN30/eMIOS18/PCS_C3 PB3/AN31/PCS_C2 PB4/AN32/PCS_C1 PB5/AN33/PCS_C0 PB6/AN34/SCK_C PB7/AN35/SOUT_C PB8/AN36/SIN_C PB9/AN37/CNTX_D/PCS_B4 PB10/AN38/CNRX_D/PCS_B3 PB11/AN39/eMIOS19/PCS_B5 PC0/eMIOS0/FR_A_TX_EN/AD24 PC1/eMIOS1/FR_A_TX/AD16 PC2/eMIOS2/FR_A_RX/TS VDDE1 VSSE1 PC3/eMIOS3/FR_DBG0 PC4/eMIOS4/FR_DBG1 PC5/eMIOS5/FR_DBG2 PC6/eMIOS6/FR_DBG3 PC7/eMIOS7/FR_B_RX PC8/eMIOS8/FR_B_TX/AD15 PC9/eMIOS9/FR_B_TX_EN/AD14 PC10/eMIOS10/PCS_C5/SCK_D PC11/eMIOS11/PCS_C4/SOUT_D
REFBYPC AN7/PA7 AN6/PA6 AN5/PA5 AN4/PA4 AN3/PA3 AN2/PA2 AN1/PA1 AN0/PA0 RESET CNTX_F/AN16/ANR/PH11 CNRX_F/AN17/ANS/PH10 CNRX_E/AN18/ANT/PH9 MA0/CNTX_E/AN19/PH8 VSSE2 VDDE2 RXD_F/AN20/PH7 TXD_F/AN21/PH6 MA1/RXD_E/AN22/PH5 MA2/TXD_E/AN23/PH4 CS2/eMIOS23/AN24/PH3 CS3/eMIOS22/AN25/PH2 SDA_A/eMIOS21/AN26/PH1 SCL_A/eMIOS20/AN27/PH0 SIN_A/AD31/PG15 SOUT_A/AD30/PG14 SCK_A/AD29/PG13 PCS_A0/AD28/PG12 PCS_A1/AD27/PG11 PCS_A2/AD26/PG10 VDD VSSE2 VDDE2 TXD_C/PCS_A3/AD25/PG9 PCS_A4/AD24/PG8 RXD_C/eMIOS23/AD23/PG7
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 LQFP
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PC12/eMIOS12/PCS_C3/SIN_D PC13/eMIOS13/PCS_A5/PCS_D0 PC14/eMIOS14/PCS_A4/PCS_D1 PC15/eMIOS15/PCS_A3/PCS_D2 PD0/CNTX_A/PCS_D3 PD1/CNRX_A/PCS_D4
PD2/CNRX_B/eMIOS10/BOOTCFG*/PCS_D5
eMIOS22/AD22/PG6 eMIOS21/AD21/PG5 PCS_C0/eMIOS20/AD20/PG4 SCK_C/eMIOS19/AD19/PG3 SOUT_C/eMIOS18/AD18/PG2 SIN_C/eMIOS17/AD17/PG1 eMIOS16/AD16/PG0 CNRX_D/TEA/WE1/PF15 CNTX_D/BDIP/WE0/PF14 VDDR VSSE2 VDDE2 RXD_D/OE/PF13 ALE/TXD_D/TS/PF12 MDO7/RXD_C/CS0/PF11 MDO6/TXD_C/CS1/PF10 VDD
* Denotes active during RESET only
Figure 2. MPC5510 Pinout - 144 LQFP
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
MDO5/ADDR15/AD15/PF9 MDO4/ADDR14/AD14/PF8 MDO3/ADDR13/AD13/PF7 MDO2/MLB_SLOT/ADDR12/AD12/PF6 MDO1/MLBDO/ADDR11/AD11/PF5 MDO0/MLBSO/ADDR10/AD10/PF4 VSSE3 VDDE3 TEST MCKO/MLBDI/ADDR9/AD9/PF3 MSEO/MLBSI/ADDR8/AD8/PF2 EVTO/MLBCLK/TA/PF1 EVTI/RD_WR/PF0 CLKOUT/PE6 JCOMP TDI TDO TCK TMS
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PD3/CNTX_B/eMIOS11 PD4/CNTX_C/eMIOS12 PD5/CNRX_C/eMIOS13 PD6/TXD_A/eMIOS14 PD7/RXD_A/eMIOS15 VDDE1 VSSE1 PD8/TXD_B/SCL_A PD9/RXD_B/SDA_A PD10/PCS_B2/CNTX_F/NMI0 PD11/PCS_B1/CNRX_F/NMI1 PD12/PCS_B0/eMIOS9 PD13/SCK_B/eMIOS8 PD14/SOUT_B/eMIOS7 PD15/SIN_B/eMIOS6 PE0/PCS_A2/eMIOS5/MLBCLK PE1/PCS_A1/eMIOS4/MLBSI PE2/PCS_A0/eMIOS3/MLBDI PE3/SCK_A/eMIOS2//MLBSO PE4/SOUT_A/eMIOS1/MLBDO PE5/SIN_A/eMIOS0/MLB_SLOT VSS/VSSF VDD/VDDF VPP VDD33/VFLASH VSSSYN EXTAL/EXTCLK XTAL VDDSYN
Pin Assignments and Reset States
1.4
Pinout - 176 LQFP
VDDA/VRH PA8/AN8/ANW PA9/AN9/ANX VSSA/VRL PA10/AN10/ANY PA11/AN11/ANZ PA12/AN12 PA13/AN13 PK0/EXTAL32 PA14/AN14 PK1/XTAL32 PA15/AN15 PB12/TXD_G/PCS_B4 PB13/RXD_G/PCS_B3 PB0/AN28/eMIOS16/PCS_C5 PB1/AN29/eMIOS17/PCS_C4 PB2/AN30/eMIOS18/PCS_C3 PB3/AN31/PCS_C2 PB4/AN32/PCS_C1 PB5/AN33/PCS_C0 PB6/AN34/SCK_C VDDE1 VSSE1 PB7/AN35/SOUT_C PB8/AN36/SIN_C PB9/AN37/CNTX_D/PCS_B4 PB10/AN38/CNRX_D/PCS_B3 PB11/AN39/eMIOS19/PCS_B5 PB14/TXD_H PB15/RXD_H PC0/eMIOS0/FR_A_TX_EN/AD24 PC1/eMIOS1/FR_A_TX/AD16 PC2/eMIOS2/FR_A_RX/TS VDDE1 VSSE1 PC3/eMIOS3/FR_DBG0 PC4/eMIOS4/FR_DBG1 PC5/eMIOS5/FR_DBG2 PC6/eMIOS6/FR_DBG3 PC7/eMIOS7/FR_B_RX PC8/eMIOS8/FR_B_TX/AD15 PC9/eMIOS9/FR_B_TX_EN/AD14 PC10/eMIOS10/PCS_C5/SCK_D PC11/eMIOS11/PCS_C4/SOUT_D
REFBYPC AN7/PA7 AN6/PA6 AN5/PA5 AN4/PA4 AN3/PA3 AN2/PA2 AN1/PA1 AN0/PA0 RESET CNTX_F/AN16/ANR/PH11 CNRX_F/AN17/ANS/PH10 SIN_D/PJ15 CNRX_E/AN18/ANT/PH9 SOUT_D/PJ14 SCK_D/PJ13 MA0/CNTX_E/AN19/PH8 PCS_D0/PJ12 PCS_D1/PJ11 VSSE2 VDDE2 RXD_F/AN20/PH7 TXD_F/AN21/PH6 MA1/RXD_E/AN22/PH5 PCS_D2/PJ10 PCS_D3/PJ9 PCS_D4/PJ8 MA2/TXD_E/AN23/PH4 CS2/eMIOS23/AN24/PH3 CS3/eMIOS22/AN25/PH2 SDA_A/eMIOS21/AN26/PH1 SCL_A/eMIOS20/AN27/PH0 SIN_A/AD31/PG15 SOUT_A/AD30/PG14 SCK_A/AD29/PG13 PCS_A0/AD28/PG12 PCS_A1/AD27/PG11 PCS_A2/AD26/PG10 VDD VSSE2 VDDE2 TXD_C/PCS_A3/AD25/PG9 PCS_A4/AD24/PG8 RXD_C/eMIOS23/AD23/PG7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
WE3/PH15 WE2/PH14 CNRX_D/TEA/WE1/PF15 CNTX_D/BDIP/WE0/PF14 VDDR VSSE2 VDDE2 RXD_D/OE/PF13 ALE/TXD_D/TS/PF12 MDO7/RXD_C/CS0/PF11 MDO6/TXD_C/CS1/PF10 VDD
MDO5/ADDR15/AD15/PF9 MDO4/ADDR14/AD14/PF8 MDO3/ADDR13/AD13/PF7 AD7/PJ7 MDO2/MLB_SLOT/ADDR12/AD12/PF6 AD6/PJ6 VSSE3 VDDE3 MDO1/MLBDO/ADDR11/AD11/PF5 AD5/PJ5 MDO0/MLBSO/ADDR10/AD10/PF4 AD4/PJ4 VSSE3 VDDE3
VSUP/TEST MCKO/MLBDI/ADDR9/AD9/PF3 MSEO/MLBSI/ADDR8/AD8/PF2 EVTO/MLBCLK/TA/PF1 EVTI/RD_WR/PF0 CLKOUT/PE6 JCOMP TDI TDO TCK TMS
eMIOS22/AD22/PG6 eMIOS21/AD21/PG5 PCS_C0/eMIOS20/AD20/PG4 SCK_C/eMIOS19/AD19/PG3 SOUT_C/eMIOS18/AD18/PG2 SIN_C/eMIOS17/AD17/PG1 eMIOS16/AD16/PG0
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
18
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
176 LQFP
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
PC12/eMIOS12/PCS_C3/SIN_D PC13/eMIOS13/PCS_A5/PCS_D0 PC14/eMIOS14/PCS_A4/PCS_D1 PC15/eMIOS15/PCS_A3/PCS_D2 PD0/CNTX_A/PCS_D3 PD1/CNRX_A/PCS_D4 PD2/CNRX_B/eMIOS10/BOOTCFG*/PCS_D5 PD3/CNTX_B/eMIOS11 PD4/CNTX_C/eMIOS12 PD5/CNRX_C/eMIOS13 PD6/TXD_A/eMIOS14 PD7/RXD_A/eMIOS15 VDDE1 VSSE1 PD8/TXD_B/SCL_A PD9/RXD_B/SDA_A PD10/PCS_B2/CNTX_F/NMI0 PD11/PCS_B1/CNRX_F/NMI1 PD12/PCS_B0/eMIOS9 PD13/SCK_B/eMIOS8 PE10 PE11 PD14/SOUT_B/eMIOS7 PE12 PE13 PD15/SIN_B/eMIOS6 PE0/PCS_A2/eMIOS5/MLBCLK VDDE1 VSSE1 PE1/PCS_A1/eMIOS4/MLBSI PE14 PE2/PCS_A0/eMIOS3/MLBDI PE3/SCK_A/eMIOS2//MLBSO PE15 PE4/SOUT_A/eMIOS1/MLBDO PE5/SIN_A/eMIOS0/MLB_SLOT VSS/VSSF VDD/VDDF VPP VDD33/VFLASH VSSSYN EXTAL/EXTCLK XTAL VDDSYN
* Denotes active during RESET only
Figure 3. MPC5510 Pinout - 176 LQFP
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Pin Assignments and Reset States
1.5
Pinout - 208 PBGA
1 A B C D E F G H J K L M N VDD REF BYPC PA7 PA5 PA2 PH13 PJ15 PH8 PH7 PJ9 PH2 PG15 PG11 2 VDDA VDD PA6 PA4 PA1 PH12 PH9 PJ12 PH6 PJ8 PH1 PG14 PG10 PG8 VDD PG6 2 3 PA8 VRH VSS PA3 PA0 PH11 PJ14 PJ11 PH5 PH4 PH0 PG13 PG9 VSS PG5 PG4 3 4 VSSA VRL PA9 VSS RESET PH10 PJ13 VDDE2 PJ10 PH3 VDDE2 PG12 VSS PG3 PG2 PG1 4 VDDE2 PG0 PH15 PH14 5 PF15 PF14 PF13 VDDR 6 PF12 PF11 PF10 PF9 7 PF8 PF7 PJ7 PF6 8 VDDE3 PJ6 PF5 PJ5 9 PJ2 PJ4 PJ3 PF4 10 PJ0 PJ1 TEST VDDE3 11 PF0 PF1 PF2 PF3 12 5 PA13 PA12 PA11 PA10 6 PK1 PK0 PA15 PA14 7 PB12 PB13 PB0 PB1 8 PB2 PB3 PB4 PB5 9 PB6 PB7 PB8 PB9 10 PB10 PB11 PB14 VDDE1 11 PB15 PC0 PC1 PC2 12 PC3 PC4 PC5 PC6 13 PC7 PC8 PC9 VSS VDDE1 PD5 PD8 PE7 PE9 PE12 PE13 PE3 VSS PE6 TDI 14 PC10 PC11 VSS PC15 PD2 PD6 PD10 PD12 PD14 PD15 PE1 PE15 PE4 VSS TCK 15 VDDE1 VDD PC13 PD0 PD3 PD7 PD11 PD13 PE11 VDDE1 PE2 PE5 16 VDD PC12 PC14 PD1 PD4 PD9 A B C D E F
208 PBGA Ball Map
(as viewed from top through the package)
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDE1 G PE8 PE10 PE0 PE14 H J K L
VSSSYN M
VDD33 EXTAL N VPP VDD TMS 15 XTAL P
P VDDE2 R T PG7 VDD 1
VDDSYN R VDD 16 T
JCOMP TDO 13 14
Figure 4. MPC5510 Pinout - 208 PBGA
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Electrical Characteristics
2
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU.
2.1
Num 1 2 3 4
Maximum Ratings
Table 3. Absolute Maximum Ratings1
Characteristic 5.0V Voltage Regulator Reference Voltage 5.0V Analog Supply Voltage (reference to VSSA) 5.0V Flash Program/Erase Voltage 3.3V - 5.0V External I/O Supply Voltage 3 VDDE14 VDDE24 VDDE34 - 0.3 - 0.3 - 0.3 -1.06 - 0.3 - 5.5 - 0.3 - VDDA -2 -3 - 55.0 -- -- 6.5 6.5 6.5 6.57 5.5 5.5 0.3 0.3 2 3 150.0 260.0 3 V V V V V mA mA
oC oC
Symbol VDDR VDDA VPP
Min - 0.3 - 0.3 - 0.3
Max2 6.5 6.5 6.5
Unit V V V V
5 6 7 8 9 10 11 12 13 14
1
DC Input Voltage 5 VREF Differential Voltage VRH to VDDA Differential Voltage VRL to VSSA Differential Voltage VDDR to VDDA Differential Voltage Maximum DC Digital Input Current (per pin, applies to all digital MH, SH, and IH pins) Maximum DC Analog Input Current 9 (per pin, applies to all analog AE and A pins) Storage Temperature Range Maximum Solder Temperature 10 Moisture Sensitivity Level 11
8
VIN VRH - VRL VRH - VDDA VRL - VSSA VDDR - VDDA IMAXD IMAXA TSTG TSDR MSL
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 All functional non-supply I/O pins are clamped to V SS and VDDE. 4V , VDDE2, and VDDE3 are separate power segments and may be powered independently with no differential voltage DDE1 constraints between the power segments. 5 AC signal over and undershoot of the input voltages of up to +/- 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 6 Internal structures will hold the input voltage above -1.0 volt if the injection current limit of 2mA is met. 7 Internal structures hold the input voltage below this maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within Operating Voltage specifications. 8 Total injection current for all pins (including both digital and analog) must not exceed 25mA. 9 Total injection current for all analog input pins must not exceed 15mA. 10 Solder profile per CDF-AEC-Q100. 11 Moisture sensitivity per JEDEC test method A112.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.2
Thermal Characteristics
Table 4. Thermal Characteristics
Value
Num 1
Characteristic Junction to Ambient Natural Convection (Single layer board)
1, 2
Symbol Unit 208 MAPBGA RJA C/W 45 176 LQFP 38 144 LQFP 43
2
Junction to Ambient 1, 3 Natural Convection (Four layer board 2s2p) Junction to Ambient 1, 3 (@200 ft./min., Single layer board) Junction to Ambient 1, 3 (@200 ft./min., Four layer board 2s2p) Junction to Board 4 Junction to Case
5 6
RJA
C/W
28
31
34
3 4 5 6 7
1
RJMA C/W RJMA C/W RJB RJC JT C/W C/W C/W
-- -- -- -- --
30 25 20 6 2
34 28 22 7 2
Junction to Package Top Natural Convection
2 3 4 5 6
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
2.2.1
General Notes for Specifications at Maximum Junction Temperature
TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) Eqn. 2 Eqn. 3 Eqn. 4 Eqn. 1
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Electrical Characteristics
the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components. Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm2. The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction to board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) Eqn. 6 Eqn. 7 Eqn. 8 Eqn. 9 Eqn. 5
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (oC/W) RJC = junction to case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) Eqn. 11 Eqn. 12 Eqn. 13 Eqn. 10
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the
MPC5510 Microcontroller Family Data Sheet, Rev. 2 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) Eqn. 15 Eqn. 16 Eqn. 17 Eqn. 14
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. 2. 3. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Electrical Characteristics
2.3
ESD Characteristics
Table 5. ESD Ratings1, 2
Characteristic Symbol Value 2000 R1 C 1500 100 500 (all pins) 750 (corner pins) V Unit V Ohm pF
ESD for Human Body Model (HBM) HBM Circuit Description
ESD for Field Induced Charge Model (FDCM)
Number of Pulses per pin: Positive Pulses (HBM) Negative Pulses (HBM) Interval of Pulses
1 2
-- -- --
1 1 1
-- -- second
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification
MPC5510 Microcontroller Family Data Sheet, Rev. 2 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.4
Num 1a
DC Electrical Specifications
Table 6. DC Electrical Specifications
Characteristic C parts Operating junction temperature range Operating ambient temperature range1 V parts Operating junction temperature range Operating ambient temperature range1 M parts Operating junction temperature range Operating ambient temperature range1 5.0V Voltage Regulator Reference Voltage 5.0V Analog Supply Voltage 5.0V Flash Program/Erase Voltage
2
Symbol
Min
Max
Unit
o o
TJ TA TJ TA TJ TA VDDR VDDA VPP VDDE13,4 VDDE23 VDDE33
- 40 - 40 - 40 - 40 - 40 - 40 4.5 4.5 4.5 3.0 3.0 3.0
105 85 120 105 145 125 5.25 5.25 5.25 5.5 5.5 5.5
C C C C C C
1b
o o
1c
o o
2 3 4 5
V V V V
3.3V - 5.0V External I/O Supply Voltage
6 7 8 9 10
Pad (SH/MH/IH) Input High Voltage Pad (SH/MH/IH) Input Low Voltage Pad (SH/MH/IH) Input Hysteresis Analog (AE/A) Input Voltage Slow/Medium I/O Output High Voltage IOH = -1.0 mA IOH = -0.2 mA Slow/Medium I/O Output Low Voltage IOL = 1.0 mA IOH = 0.2 mA Input Capacitance (Digital Pins: Pad type MH,SH, IH with no A or AE) Input Capacitance (Analog Pins: Pad type A, AE, and AE+IH) Input Capacitance (Shared digital and analog pins: A with SH or MH) Slow/Medium I/O Weak Pull Up/Down Absolute Current 5 I/O Input Leakage Current
6
VIH VIL VHYS VINDC VOH
0.65 x VDDE VDDE + 0.3 VSS - 0.3 0.35 x VDDE
V V V V V
0.1 x VDDE 0.2 x VDDE VSSA - 0.3 VDDA + 0.3 see note4 0.80 x VDDE 0.95 x VDDE -- --
11
VOL
V 0.20 x VDDE 0.05 x VDDE 7 10 12 170 1.5 2.0 200 1.5 100 pF pF pF A A mA nA A mV
12 13 14 15 16 17 18 19 20
CIN CIN_A CIN_M IACT IINACT_D IIC
-- -- -- 10 - 1.5 - 2.0 - 200 -1.5 - 100
DC Injection Current (per pin) Analog Input Current, Channel Off (Analog pins AE and AE+IH) Analog Input Current (Shared digital and analog pins: A with SH or MH) VRH to VDDA Differential Voltage
7
IINACT_A IINACT_AD VRH - VDDA
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Electrical Characteristics
Table 6. DC Electrical Specifications (continued)
Num 21 22 23 24 25 26 Characteristic VRL to VSSA Differential Voltage VSS to VSSA Differential Voltage VSSSYN to VSS Differential Voltage VDDR to VDDA Differential Voltage Slew rate on VDDA, VDDR, and VDDE power supply pins Capactive Supply Load VDD VDD33 VDDSYN Symbol VRL - VSSA VSS - VSSA VSSSYN - VSS VDDR - VDDA Vramp Vload 800 200 200 -- -- Min - 100 - 100 -50 - 100 1 Max 100 100 50 100 100 Unit mV mV mV mV V/ms nF
1 2 3 4 5 6 7
Please refer to Section 2.2.1, "General Notes for Specifications at Maximum Junction Temperature" for more details about the relation between ambient temperature TA and device junction temperature TJ. VPP can drop to 0 volts during read-only operations and before entry to Sleep mode, to reduce power consumption. VDDE1, VDDE2, and VDDE3 are separate power segments and may be powered independently with no differential voltage constraints between the power segments. If VDDE1 is below VDDA than the analog input limits (spec #9 (Analog (AE/A) Input Voltage) in Table 6) will be based on the VDDE1 voltage level. Absolute value of current, measured at VIL and VIH. Weak pull up/down inactive. Measured at VDDE = 5.25 V. Applies to pad types: SH and MH. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: A and AE.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.5
Operating Current Specifications
Table 7. Operating Currents
Typ1 Max1 Typ1 25C 70C -40-145C Ambient Ambient Junction
Num
Characteristic
Symbol
Unit
Equations 1
ITOTAL = IDDE + IPP + IDDA + IDDR IDDE = IDDE1 + IDDE2 + IDDE3 VDDE(1,2,3) Current VDDE(1,2,3) @ 3.0V - 5.5V Static2, or when in SLEEP or STOP Dynamic3 VPP Current VPP @ 0V (All modes) VPP @ 5.25V SLEEP mode STOP mode RUN mode VDDA Current VDDA @ 4.5V - 5.25V RUN mode4 SLEEP/STOP5 mode with 32KIRC SLEEP/STOP5 mode with 32KOSC SLEEP/STOP5 mode with 16MIRC VDDR Current VDDR@ 4.5V - 5.25V SLEEP mode STOP mode RUN mode (Using 16 MHz IRC) RUN mode (Maximum @ 48 MHz)6 RUN mode (Maximum @ 66 MHz)7 RUN mode (Maximum @ 80MHz)8 Optional: RTC/API (SLEEP mode) Optional: Each 8K RAM block (SLEEP mode) Optional: XOSC (SLEEP and STOP mode)9 IDDE 1 Note 3 IPP 1 15 15 1 IDDA 5 12 12 111 IDDR 20 170 30 50 105 120 1 0.8 500 25 600 35 75 110 130 1 7 600 360 4200 40 90 120 135 3 45 900 A A mA mA mA mA A A A 5 16 16 165 10 26 28 225 mA A A A 1 20 20 1 1 30 30 25 A A A mA 3 Note 3 30 Note 3 A mA
2
3
4
1 2
3 4 5 6 7
Typ - Nominal voltage levels and functional activity. Max - Maximum voltage levels and functional activity. Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads. Dynamic current from pins is application specific and depends on active pull devices, switching outputs, output capacitive and current loads, and switching inputs. Refer to Table 8 for more information. RUN mode is a typical application with the ADC, 16MIRC, 32KIRC running. SLEEP/STOP mode means that only the listed peripherals are on. All others are diabled. RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal, all peripherals enabled, both cores running, and running a typical application using both SRAM and flash. RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal; all peripheral and cores enabled and running a typical application using both SRAM and flash. Be sure to calculate the junction temperature, as the maximum current at maximum ambient temperature can exceed the maximum junction temperature.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Electrical Characteristics
8
RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal, all peripheral and cores enabled and running a typical application using both SRAM and flash. Only for 208 MAPBGA or lower ambient 144 pin and only 120C junction or lower. Be sure to calculate the junction temperature, as the maximum current at maximum ambient temperature can exceed the maximum junction temperature 9 XOSC: optionally enabled in SLEEP and STOP modes (oscillator remains running from crystal but XOSC clock output disabled).
MPC5510 Microcontroller Family Data Sheet, Rev. 2 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.6
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 8 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 8. Table 8. I/O Pad Average DC Current1
Num 1 2 3 4 5 6 7 8
1 2
Pad Type Slow (Pad Type SH)
Symbol IDRV_SH
Frequency (MHz) 25 10 2 2
Load2 (pF) 50 50 50 200 50 50 50 200
Voltage (V) 5.25 5.25 5.25 5.25 5.25 5.25 5.25 5.25
Slew Rate Control 11 01 00 00 11 01 00 00
Current (mA) 8.0 3.2 0.7 2.4 17.3 6.5 1.1 3.9
Medium (Pad Type MH)
IDRV_MH
50 20 3.33 3.33
These values are estimated from simulation and are not tested. Currents apply to output pins only. All loads are lumped.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Electrical Characteristics
2.7
Num 1 2
Low Voltage Characteristics
Table 9. Low Voltage Monitors
Characteristic Power-on-Reset Assert Level 1 Low Voltage Monitor 1.5V 1 Assert Level De-assert Level Low Voltage Monitor 3.3V 2 Assert Level De-assert Level Low Voltage Monitor Synthesizer 3 Assert Level De-assert Level Low Voltage Monitor 5.0V Low Threshold 4 Assert Level De-assert Level Low Voltage Monitor 5.0V 4 Assert Level De-assert Level Low Voltage Monitor 5.0V High Threshold 4 Assert Level De-assert Level Symbol VPOR VLV15A VLV15D VLV33A VLV33D VLVSYNA VLVSYND VLV5LA VLV5LD VLV5A VLV5D VLV5HA VLV5HD Min 0.30 -- -- -- -- -- -- 3.30 3.35 4.50 4.55 4.70 4.75 Typical 0.70 1.40 1.45 3.05 3.10 3.05 3.10 3.35 3.40 4.55 4.60 4.75 4.80 Max 0.90 -- -- -- -- -- -- 3.40 3.45 4.70 4.75 4.80 4.85 Unit V V
3
V
4
V
5
V
6
V
7
V
1 2
Monitors VDD Monitors VDD33 3 Monitors V DDSYN 4 Monitors V DDA
MPC5510 Microcontroller Family Data Sheet, Rev. 2 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.8
Num 1 2 3
Oscillators Electrical Characteristics
Table 10. 3.3V High Frequency External Oscillator
Characteristic Frequency Range1 Duty Cycle of reference EXTAL Input High Voltage External crystal mode 3 External clock mode EXTAL Input Low Voltage External crystal mode 3 External clock mode XTAL Current 4 Total On-chip stray capacitance on XTAL Total On-chip stray capacitance on EXTAL Crystal manufacturer's recommended capacitive load Discrete load capacitance to be connected to EXTAL Discrete load capacitance to be connected to XTAL Startup Time Symbol fref tdc VIHEXT VXTAL + 0.4 0.65 x VDDSYN VILEXT VDDSYN - 0.3 VDDSYN - 0.3 IXTAL CS_XTAL CS_EXTAL CL CL_EXTAL CL_XTAL tstartup 2 -- -- See crystal specification -- -- -- VXTAL - 0.4 0.35 x VDDSYN 6 3 3 See crystal specification 2xCL - CS_EXTAL - CPCB_EXTAL5 2xCL - CS_XTAL - CPCB_XTAL5 10 mA pF pF pF pF pF ms VDDSYN + 0.3 VDDSYN + 0.3 V Min. Value 42 40 Max. Value 40 60 Unit MHz % V
4
5 6 7 8 9 10 11
1 2 3 4 5
Since this is an amplitude controlled oscillator the use of overtone oscillators is not recommended. Only use fundamental frequency oscillators. When PLL frequency modulation is active, reference frequencies less than 8MHz will distort the modulated waveform and the effects of this on emissions is not characterized. This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vextal - Vxtal 400mV criteria has to be met for oscillator's comparator to produce output clock. Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively
Table 11. 5V Low Frequency (32 kHz) External Oscillator
Num 1 2 3 4 5
1
Characteristic Frequency Range Duty Cycle of reference XTAL32 Current
1
Symbol fref32 tdc32 IXTAL32 CL32 tstartup
Min. Value 32 40 0.5 See crystal specification --
Max. Value 38 60 3 See crystal specification 2
Unit kHz % A pF s
Crystal manufacturer's recommended capacitive load Startup Time
Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Electrical Characteristics
Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator
Num 1 2 3 4 5
1 2
Characteristic Frequency before trim1 Frequency after loading factory trim2 Application trim resolution3 Application frequency trim step3 Start up time
Symbol Fut Ft Ts Fs St
Min 12.8 15.1 -- -- --
Typ 16 16 -- 300 --
Max 22.3 16.9 0.5 -- 500
Unit MHz MHz % kHz ns
Across process, voltage, and temperature Across voltage and temperature 3 Fixed voltage and temperature
Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator
Num 1 2 3 4 5
1 2
Characteristic Frequency before trim1 Frequency after loading factory trim2 Application trim resolution3 Application frequency trim step3 Start up time
Symbol Fut32 Ft32 Ts32 Fs32 St32
Min 20.8 26 -- -- --
Typ 32.0 32.0 -- 1 --
Max 43.2 38 2 -- 100
Unit kHz kHz % kHz s
Across process, voltage, and temperature Across voltage and temperature 3 Fixed voltage and temperature
MPC5510 Microcontroller Family Data Sheet, Rev. 2 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.9
Num 1
FMPLL Electrical Characteristics
Table 14. FMPLL Electrical Specifications 1
Characteristic System frequency2 -40 oC TJ 120 oC -40 oC TJ 145 oC PLL Reference Frequency (output of predivider) VCO Frequency4
5
Symbol fsys
Min. Value 375 375
Max. Value 80000 3 66000 10 500 80 3 66 1000 35 750 4.0 2.0 5 2 3
Unit kHz
2 3 4
fpllref fvco fpll
4 192 3 3
MHz MHz MHz
PLL Frequency -40 oC TJ 120 oC -40 oC TJ 145 oC Loss of Reference Frequency 6 Self Clocked Mode Frequency PLL Lock Time
8 7
5 6 7 8 9 10 11 12
1 2
fLOR fSCM tlpll fUL fLCK Cjitter
11,12
100 13 -- - 4.0 - 2.0 -5 0.5 1
kHz MHz s % fsys % fsys % fclkout %fsys %fsys
Frequency un-LOCK Range Frequency LOCK Range CLKOUT Cycle-to-cycle Jitter,9, 10
Frequency Modulation Depth 1% Setting (fsysMax must not be exceeded)
Cmod Cmod
Frequency Modulation Depth 2% Setting 11,12 (fsysMax must not be exceeded)
VDDSYN = 3.0V to 3.6 V, VSSSYN = 0 V, TA = TL to TH The maximum value is without frequency modulation turned on. If frequency modulation is turned on, the maximum value (average frequency) must be de-rated by the percentage of modulation enabled. 3 80 MHz is not available in the 176 pin package. 4 Optimum performance is achieved with the highest VCO frequency feasible based on the highest ERFD that results in the desired PLL frequency. 5 The VCO frequency range is higher than the maximum allowable PLL frequency. The synthesizer control register 2's enchanced reduced frequency divider (FMPLL_SYNCR2[ERFD]) in enhanced operation mode must be programmed to divide the VCO frequency within the PLL frequency range. 6 Loss of reference frequency is the reference frequency detected by the PLL which then transitions into self clocked mode. 7 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f LOR. 8 This specification applies to the period required for the PLL to relock after changing the enhanced multiplication factor divider (EMFD) bits in the synthesizer control register 1 (SYNCR1) in enhanced operation mode. 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider set to divide-by-2. 10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod. 11 Modulation depth selected must not result in f sys value greater than the fsys maximum specified value. 12 These depth ranges are obtained by filtering the raw cycle-to-cycle clock frequency data to eliminate the presence of the the normal clock jitter riding on top of the FM waveform. The allowable modulation rates are 400 kHz to 1 MHz.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Electrical Characteristics
2.10
Num 1 2 3 4 5 6 7 8 9 10
eQADC Electrical Characteristics
Table 15. eQADC Conversion Specifications (Operating)
Characteristic ADC Clock (ADCLK) Frequency1 Conversion Cycles Stop Mode Recovery Time2 Resolution INL: 12 MHz ADC Clock3
3
Symbol FADCLK CC TSR -- INL12 DNL12 OFFWC GAINWC IINJ EINJ
Min 1 14+2 (or 16) 20 1.25 -- -- -- -- -- --
Max 12 14+128 (or 142) -- -- 10 10 10 10 1 6
Unit MHz ADCLK cycles s mV Counts Counts Counts Counts mA Counts
DNL: 12 MHz ADC Clock Offset Error with
Calibration3 Current 4, 5, 6, 7
Full Scale Gain Error with Calibration Disruptive Input Injection
Incremental Error due to injection current. All channels have same 10k < Rs <100k 3 Channel under test has Rs=10k, IINJ=IINJMAX,IINJMIN Total Unadjusted Error for single ended conversions with calibration3, 8, 9, 10 Source Impedance11
11 12
1
TUE RS
-- --
10 100k
Counts Ohm
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a maximum 16 factor. 2 The specified value is for the case when the 100nF capacitor is not connected to the REFBYPC pin. When the capacitor is connected to the REFBPYC pin, the recovery time is 10ms. 3 At V RH - VRL = 5.12 V, one lsb = 1.25 mV = one count, this is an additional count error to the TUE count error. 4 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 5 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = - 0.3 V, then use the larger of the calculated values. 7 Condition applies to two adjacent pads on the internal pad. 8 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors. 9 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref) 10 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification) may affect the actual TUE measured on analog channels shared digital pins. 11 If R is greater than 1 k Ohm, be sure to calculate the affect of pin leakage and use the proper sampling time, to ensure that S you get the accuracy required.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.11
Num 1 2 3 4 5 6 7
Flash Memory Electrical Characteristics
Table 16. Flash Program and Erase Specifications1
Characteristic Double Word (64 bits) Program Time 4 Page (128 bits) Program Time
4
Symbol Tdwprogram Tpprogram T16kpperase T64kpperase T128kpperase -- Trwsc
Min -- -- -- -- -- 25
Typ 10 15 325 525 675 --
Initial Max2 -- 44 525 675 1800 --
Max3 500 500 5000 5000 7500 --
Unit s s ms ms ms MHz MHz
16 Kbyte Block Pre-program and Erase Time 64 Kbyte Block Pre-program and Erase Time 128 Kbyte Block Pre-program and Erase Time Minimum operating frequency for program and erase operations Wait States Relative to System Frequency PFCRPn[RWSC] = 0b000; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = 0b001; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = 0b010; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = 0b011; PFCRPn[WWSC] = 0b01 Recovery Time Stop mode exit or STOP bit negated Sleep mode exit (with CRP_RECPTR[FASTREC]=1) 5
-- -- -- -- Trecover -- --
-- -- -- -- -- --
-- -- -- -- -- --
25 50 75 80 20 120 s s
8
1
2
Typical program and erase times assume nominal supply values and operation at 25 oC. Initial factory condition: < 100 program/erase cycles, nomial supply values and operation at 25 oC. 3 The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 This does not include software overhead. 5 If CRP_RECPTR[FASTREC]=0, then hardware will wait 2340 system clocks before exiting from Sleep mode to account for the flash recovery time. The default system clock source after Sleep is the 16MIRC. A nominal frequency of 16MHz equates to a hardware wait of 146s.
Table 17. Flash EEPROM Module Life (Full Temperature Range)
Num 1 Characteristic Number of Program/Erase cycles per block over the operating temperature range (TJ) 16 Kbyte and 64 Kbyte blocks 128 Kbyte blocks Data retention Blocks with 0 - 1,000 P/E cycles Blocks with 1,001 - 100,000 P/E cycles Symbol P/E 100,000 1000 Retention 20 5 -- 100,000 -- years Min Typical1 Unit cycles
2
1
Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 "Typical Endurance for Nonvolatile Memory."
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Electrical Characteristics
2.12
Num 1
Pad AC Specifications
Table 18. Pad AC Specifications (VDDE = 3.0V - 5.5V)1
Pad Type Slow (SH) SRC 11 Out Delay2, 3 (ns) 39 120 01 101 188 00 507 597 Rise/Fall3, 4 (ns) 23 87 52 111 248 312 12 44 22 50 123 156 7500 9500 Load Drive (pF) 50 200 50 200 50 200 50 200 50 200 50 200 50 50
2
Medium (MH)
11
23 64
01
50 90
00
261 305
4 5
1
Pull Up/Down (3.6V max) Pull Up/Down (5.5V max)
-- --
-- --
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDDE = 3.0V to 5.5V, TA = TL to TH. 2 This parameter is supplied for reference and is not tested. Add a maximum of one system clock to the output delay for delay with respect to system clock. 3 Delay and rise/fall are measured to 20% or 80% of the respective signal. 4 This parameter is guaranteed by characterization before qualification rather than 100% tested.
VDD/2 Pad Internal Data Input Signal Rising Edge Out Delay Falling Edge Out Delay VOH
Pad Output
VOL
Figure 5. Pad Output Delay
MPC5510 Microcontroller Family Data Sheet, Rev. 2 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.13
2.13.1
Num 1 2 3
AC Timing
Reset and Boot Configuration Pins
Table 19. Reset and Boot Configuration Timing
Characteristic RESET Pulse Width BOOTCFG Setup Time after RESET Valid BOOTCFG Hold Time from RESET Valid Symbol tRPW tRCSU tRCH Min 150 -- 0 Max -- 100 -- Unit ns s s
RESET
1
2
BOOTCFG
3
Figure 6. Reset and Boot Configuration Timing
2.13.2
Num 1 2 3
1
External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins
Table 20. IRQ/NMI Timing
Characteristic Symbol tIPWL TIPWH tICYC Min 3 3 6 Max -- -- -- Unit tSYS tSYS tSYS
IRQ/NMI Pulse Width Low IRQ/NMI Pulse Width High IRQ/NMI Edge to Edge Time1
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
IRQ/NMI
1,2 3
1,2
Figure 7. IRQ and NMI Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Electrical Characteristics
2.13.3
Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1
JTAG (IEEE 1149.1) Interface
Table 21. JTAG Interface Timing1
Characteristic Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Min 100 40 -- 5 25 -- 0 -- 100 40 -- -- -- 50 50 Max -- 60 3 -- -- 20 -- 20 -- -- 50 50 50 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TCK Cycle Time TCK Clock Pulse Width (Measured at VDDE/2) TCK Rise and Fall Times (40% - 70%) TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TCK Low to TDO High Impedance JCOMP Assertion Time JCOMP Setup Time to TCK Low TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 30pF with SRC = 0b11.
TCK 2 3 2
1
3
Figure 8. JTAG Test Clock Input Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 9. JTAG Test Access Port Timing
TCK
10 JCOMP
9
Figure 10. JTAG JCOMP Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Electrical Characteristics
TCK
11
13
Output Signals
12
Output Signals 14 15
Input Signals
Figure 11. JTAG Boundary Scan Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.13.4
Num 1 2 3 4 5 6 7 8 9 10 11 12
1
Nexus Debug Interface
Table 22. Nexus Debug Port Timing1
Characteristic Symbol tMCYC tMDC
2 2
Min 40 40 -2 -2 -2 4.0 1 40 40 8 4 0
Max -- 60 4.0 4.0 4.0 --
Unit ns % ns ns ns tTCYC tMCYC ns % ns ns ns
MCKO Cycle Time MCKO Duty Cycle MCKO Low to MDO Data Valid
tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV
MCKO Low to MSEO Data Valid MCKO Low to EVTO Data Valid EVTI Pulse Width EVTO Pulse Width TCK Cycle Time TCK Duty Cycle TDI, TMS Data Setup Time TDI, TMS Data Hold Time TCK Low to TDO Data Valid
3
2
-- 60 -- -- 8
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 30pF with SRC = 0b11. 2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 The system clock frequency needs to be three times faster that the TCK frequency.
1 2 MCKO
4 5 MDO MSEO EVTO
3
Output Data Valid
Figure 12. Nexus Output Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
Electrical Characteristics
TCK
10 11
TMS, TDI
12
TDO
Figure 13. Nexus TDI, TMS, TDO Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.13.5
Num 1 2 3 4 5 6 7 8 9 10
1 2
External Bus Interface (EBI)
Table 23. External Bus Operation Timing1
Characteristic Symbol TC tCDC tCRT tCFT tCOH tCOV tCIS tCIH tALEPWH tALEAD Min 40.0 45% -- -- 2.0 -- 20.0 0 20 2 Max -- 55% -- --
3 3
Unit ns TC ns ns ns ns ns ns ns ns
CLKOUT Period2 CLKOUT duty cycle CLKOUT rise time CLKOUT fall time CLKOUT Positive Edge to Output Signal Invalid or High Z (Hold Time) CLKOUT Positive Edge to Output Signal Valid (Output Delay) Input Signal Valid to CLKOUT Posedge (Setup Time) CLKOUT Posedge to Input Signal Invalid (Hold Time) ALE Pulse Width High Time ALE Fall to AD Invalid
-- 10.0 -- -- -- --
EBI timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 50pF with SIU_PCRn[SRC] = 0b11. Initialize SIU_ECCR[EBDF] to meet maximum external bus frequency. 3 Refer to Medium High Voltage (MH) pad AC specification in Table 18.
Voh_f VDDE/2 CLKOUT Vol_f 3 2 2 4 1
Figure 14. CLKOUT Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43
Electrical Characteristics
CLKOUT
VDDE/2
6 5 5 VDDE/2
OUTPUT BUS AD[0:31] ADDR[8:15]
VDDE/2
6 5 OUTPUT SIGNAL BDIP CS[0:3] OE RD_WR TA TEA TS WE[0:3] 5
VDDE/2
6
VDDE/2
Figure 15. Synchronous Output Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 44 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDDE/2
7 8
INPUT BUS AD[0:31]
VDDE/2
7 INPUT SIGNAL RD_WR TA TEA TS 8
VDDE/2
Figure 16. Synchronous Input Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 45
Electrical Characteristics
CLKOUT
VDDE/2
TS
10
AD[0:31]
VDDE/2
9
ALE VDDE/2
Figure 17. Address Latch Enable (ALE) Timing
2.13.6
Num 1 2
Enhanced Modular I/O Subsystem (eMIOS)
Table 24. eMIOS Timing
Characteristic eMIOS Input Pulse Width eMIOS Output Pulse Width Symbol tMIPW tMOPW Min 4 1 Max -- -- Unit tCYC tCYC
MPC5510 Microcontroller Family Data Sheet, Rev. 2 46 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2.13.7
Deserial Serial Peripheral Interface (DSPI)
Table 25. DSPI Timing1
66 MHz
Num 1 2 3 4 5 6 7 8 9 SCK Cycle TIme2,3 PCS to SCK Delay After SCK Delay5
4
Characteristic
Symbol Min tSCK tCSC tASC tSDC tA tDIS tPCSC tPASC tSUI 35 5 5 35 tHI -4 10 26 -4 tSUO -- -- -- -- tHO -15 5.5 0 -15 -- -- -- -- 15 35 30 15 -- -- -- -- -- -- -- -- 60 20 20 tSCK/2 -2ns -- -- 4 5 Max -- -- -- tSCK/2 + 2ns 25 25 -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SCK Duty Cycle Slave Access Time (SS active to SOUT driven) Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) PCSx to PCSS time PCSS to PCSx time Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA=0) Master (MTFE = 1, CPHA=1) Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
10
11
12
1 2 3 4 5 6
DSPI timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 50pF with SRC = 0b11. The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two MPC55xx devices communicating over a DSPI link. The actual minimum SCK Cycle Time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK] The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC] This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 47
Electrical Characteristics
2 PCSx 4 SCK Output (CPOL=0) 4 1
3
SCK Output (CPOL=1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Figure 18. DSPI Classic SPI Timing -- Master, CPHA = 0
PCSx
SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Figure 19. DSPI Classic SPI Timing -- Master, CPHA = 1
MPC5510 Microcontroller Family Data Sheet, Rev. 2 48 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
2 SS 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Figure 20. DSPI Classic SPI Timing -- Slave, CPHA = 0
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 21. DSPI Classic SPI Timing -- Slave, CPHA = 1
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 49
Electrical Characteristics
3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Figure 22. DSPI Modified Transfer Format Timing -- Master, CPHA = 0
PCSx
SCK Output (CPOL=0)
SCK Output (CPOL=1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Figure 23. DSPI Modified Transfer Format Timing -- Master, CPHA = 1
MPC5510 Microcontroller Family Data Sheet, Rev. 2 50 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
SS
2 1
3
SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Figure 24. DSPI Modified Transfer Format Timing -- Slave, CPHA = 0
SS
SCK Input (CPOL=0)
SCK Input (CPOL=1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 25. DSPI Modified Transfer Format Timing -- Slave, CPHA = 1
7 PCSS PCSx 8
Figure 26. DSPI PCS Strobe (PCSS) Timing
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 51
Package Information
3
Package Information
The latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/powerpc. The following table lists the package case number per device. Use these numbers in the web page's "keyword" search engine to find the latest package outline drawings. Table 26. Package Information
Package 144 LQFP 176 LQFP 208 MAPBGA Package Case Number 98ASS23177W 98ASS23479W 98ARS23882W
4
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/powerpc.
MPC5510 Microcontroller Family Data Sheet, Rev. 2 52 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Product Documentation
4.1
Revision History
Table 27. Revision History of MPC5510 Data Sheet
Table 27 summarizes revisions to this document.
Revision Rev. 0 Rev. 1
Date 9/2007 6/2008 Initial Release. Preliminary content.
Substantive Changes
(Note: Change descriptions refer to locations in Rev. 0.) Changed MPC5516 to MPC5510 Family where appropriate. Modified Figure 1. MPC5510 Family Block Diagram. Deleted Table 1. MPC5510 Family Comparison, Maximum Feature Set Deleted Table 2. MPC5510 Peripheral Multiplexing Examples Corrected PK0 and PK1 pin assignments on 208 MAPBGA (Table 3 and Figure 4). Modified Table 4, footnote 4. Modified Table 8. DC Electrical Specifications and table footnotes. Modified Table 9. Operating Currents and table footnotes. Modified Table 12. 3.3V High Frequency External Oscillator, row 5. Modified Table 14. 5V High Frequency (16 MHz) Internal RC Oscillator, row 2. Modified Table 16. FMPLL Electrical Specifications, row 4. Modified Table 17. eQADC Conversion Specifications (Operating) and table footnotes. Modified Table 18. Flash Program and EraseSpecifications, row 5. Modified Table 19. Flash EEPROM Module Life (Full Temperature Range), row 1 Modified Table 28. Package Information. (Note: Change descriptions refer to locations in Rev. 1.) Modified Table 1. MPC5510 Signal Properties: added note to TEST signal. Modified Table 6. DC Electrical Specifications: rows 1b, 5, 8, 9, 10, 11, 16, 19, 25, and footnotes. Modified Table 7. Operating Currents: Max column header, rows 1, 2, 3, 4, and footnotes. Modified Table 9. Low Voltage Monitors: rows 2, 3, 4, 6. Modified Table 10. 3.3V High Frequence External Oscillator: row 1 added footnote, removed duplicate footnote #3. Modified Table 11. 5V Low Frequency (32 kHz) External Oscillator: row 1. Modified Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator: row 2. Modified Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator: row 2. Modified Table 14. FMPLL Electrical Specifications: rows 1 and 4; added two new rows. Modified Table 15. eQADC Conversion Specifications (Operating): rows 5, 6, 7, 8, 10, 11, and footnotes. Modified Figure 5. Pad Output Delay: moved the dashed horizontal line up so that it crosses the signal midway between top and bottom.
Rev. 2
12/2008
MPC5510 Microcontroller Family Data Sheet, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 53
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Document Number: MPC5510
Rev. 2 12/2008
Preliminary--Subject to Change Without Notice

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